通信工程文献翻译——随着半导体技术发展速度越来越高，系统性能受到限制不是因为单个逻辑元素和互联信号的延迟，而是因为同步数字信号流量的能力。不同的同步策略已被考虑，从完全异步到完全同步。然而，行业内占主导地位的同步策略将继续是完全同步的时钟系统。系统大小不一，从中等规模的电路到大百万晶体管微处理器和使用时需要高速，高可靠的时钟分配网络完全同步操作的超高速超级计算机。在这些高复杂性分配时钟信号中，高速处理器时构建高性能同步数字系统的一个主要局限。更让人引起注意的是被放置在时钟分配网络的大型VLSI的系统设计。

在一个同步系统中，每个数字信号通常被锁存储在一个处于锁存状态的双稳态寄存器来等待输入的时钟信号，它决定了数字信号和时离开寄存器。一旦时钟信号到达寄存器，数字信号通过组合网络离开双稳态寄存器在一个正常工作的系统中传输，进入下一个寄存器，并在下一个时钟信号出现之前被完全锁定到该寄存器中。因此，延时器件组成的普通的同步系统是由以下三个子系统组成的：（1）存储器的存储元件；（2）逻辑元件；（3）时钟电路和分销网络。同步数字系统中的三个子系统之间的互相关系是实现其性能和可靠性的重要因素。

在高性能时钟分配网络领域中，一些基本的话题也就包含在这个特殊的问题中，这个特殊的问题是有多种学术和工业机构组成的。另外，这些文件可以在三个主要领域进行分组，第一个主题主要涉及利用时钟歪斜的局部性质；第二个主题主要处理这些时钟分配网络的实施；而第三个主题主要认为下一代时钟分配网络将会达到更多更远的射程。

直到最近，时钟便宜被认为是一个全球性问题，而不是局部地区才有的。时钟歪斜的预算是跨系统的，允许时钟偏斜的特点中是从时钟周期减去的。这种设计角度歪曲了时钟偏斜的性质，它没有认识到时钟歪斜是地区性的，是针对特点的本地数据路径。此外，如果数字信号和时钟信号彼此在相同的方向上流动（即负时钟偏差）比赛条件可能是会丢失创建（即时钟信号会到达寄存器和当前数字信号到达并成功锁定之前，先前的数据信号移出寄存器）。因此，策略最近才开发的，不仅确保了这些竞争条件不存在，而且还利用本地化的时钟偏移，以便信号在最坏情况下的路径到达提供附加的时间并在该本地数据路径的最后一个寄存器中进行设置。有效地允许同步系统工作在更高的时钟频率，因此，每个数据路径的局部时钟歪斜被选择用来最小化整个系统的时钟周期，同时确保没有竞争条件存在，为每个本地数据路径确定一组本地时钟的过程倾斜成为时钟偏差调度或时钟偏移以及被用于提取被称之为......

As semiconductor technologies operate at increasingly higher speeds, system performance ha -s become limited not by the delays of the individual logic elements and interconnect but by the ability to synchronize the flow of the data signals. Different synchronization strategies have been considered,ranging from completely asynchronousto fully synchronous.However,the dominant sy -nch ronization strategy within industry will continue to be fully synchronous clocked systems. Sy -stems ranging in size from medium scale circuits to large multimillion transistor microprocessors and ultar-high speed supercomputers utilize fully synchronous operation which require high speed and highly reliable clock distribution networks. Distributing the clock signals within these high complexity,high speed processers is one of the primary limitations to building high performance synchro -nous digital systems.Greater attention is therefore being placed on the design of clock distribution networks for large VLSI-based systems.

In a synchronous digital system, the clock signal is used to de?ne the time reference for the movement of data within that system. Since this function is vital to the operation of a synchronous system, much attention has been given to the characteristics of these clock signals and the networks used in their distribution. Clock signals are often regarded as simple control signals; however, these signals have some very special characteristics and attributes.Clock signals are typically loaded with the greatest fanout, travel over the greatest distances, and operate at the highest speeds of any signal, either control or data, within the entire system. Since the data signals are provided with a temporal reference by the clock signal, the clock waveforms must be particularly clean and sharp. Furthermore,these clock signals are strongly affected by technology scaling in that long global interconnect lines become highly resistive as line dimensions are decreased. This increased line resistance is one of the primary reasons for the increasing signi?cance of clock distribution networks on synchronous performance. The control of any differences in the delay of the clock signals can also severely limit the maximum performance of the entire system and create catastrophic race conditions in which an incorrect data signal may latch within a register.

In a synchronous system, each data signal is typically stored in a latched state within a bistable register awaiting the incoming clock signal, which determines when the data signal leaves the register. Once the enabling clock signal reaches the register, the data signal leaves the bistable register and propagates through the combinatorial network,and for a properly working system, ......